A note on HooVorNet Memory Performance.

A feature of my HoovorNet is it’s minimal use of dynamic memory. Take a look at my general architecture for HooVorNet below. The input is 256 x 256 x 3 and the output is 16 x 16 x 768. If you carry through those multiplications you will find that 256 x 256 x 3 = 16 x 16 x 768, which means the output uses the same memory as the input, and if you look closely then you will see that the largest use of memory is the output of the first feature generator which is only 150% of the input memory. And HooVorNet doesn’t employ any sort of bottlenecks or hidden memory expansions. This max pipeline memory for HooVorNet is 75% the max memory used by MobileNetV2. The parameter memory is quite small at around 4700% of the size of the input image, but not as small as some of the implementations of Mobilenetv2. This means that the static parameter memory of my HooVorNet is larger, but the dynamic pipeline memory use can be smaller, which I believe means that it is possible that more pipelines of HooVorNet could be simultaneously processed in parallel on hardware then could be with MobileNetV2 pipelines.

HooVorNet: The Hints of Ozone Vortal Network

I’ve decided to call my segmentation network HooVorNet, and I’ll share some its key unique features. HooVorNet employs feature generator blocks that split filters among several calculation paths and then recombine with concatenation. HooVorNet’s feature generator blocks are distinct from other feature concentrators that use a similar method such as Google’s Inception Module because HooVorNet uses shallow and deep auto-encoders in each of the split paths, and incorporates a skip connection by concatenation.

Using the HooVorNet Feature Generator block, the network simultaneously gains the benefits of normal convolutional feature examination and the incredibly deep inference of chained auto-encoders. This block encodes shallow swept local features (1×1,3×3, and 5×5) and deep strided features (16×16).

The network employs special and undisclosed deep feature generator blocks just ahead of the output that are a more advanced version of the Feature Generator Blocks that provide the same benefits while keeping parameter and FLOP counts of the network at a minimum. For this particular embodiment of HooVorNet, the full model has only 9 million parameters and requires 4 billion floating point operations.

The LM3524D

The Texas Instruments LM3524D is a beautiful tool that I’ve been looking for for some time now. I saw a few designs based on them in school but I couldn’t recall the number or the right name when I got back into electronics. I’d search for “voltage dependent PWM generator” and the like, but I couldn’t find the right chip.

That right chip is the LM3524D. A beautiful design incorporating just about all of the sub circuits one needs to produce a controlled PWM signal. Its got an astable oscillator to serve as the signal source, tunable with your choice of timing resistor and capacitor. This replaces a 555. Its got two separate voltage differential feedback amplifiers. One is set to operate in mV range for use with current sense resistors, and this one overrides the other which is typicaly used to set a target output voltage. Finally, it permits override of both feedback controls with a single pin voltage analog input that can be used to directly set the PWM duty cycle which is linear with respect to the applied voltage. These features replace a slew of opamps and logic circuits.

The output of the circuit isn’t a regular PWM wave, interestingly enough. Rather, the internal PWM is fed into the base of a BJT, and the inverse of the PWM is fed into the base of a second BJT. This permits a certain level of direct low power usage, and more importantly permits darlington pairing with higher power BJTs, and of course, the transistors can be used to reproduce a PWM voltage signal for distribution to FET gates.

Cost Savings Placeholders in Process Development

It’s easy to get caught up in “get it working” fever and be so focused as to have an attitude of, if it works: don’t touch it. But this attitude can just be a way to reduce mental effort while working on multiple higher priority issues. This is highly reasonable, but, it can also be expensive, as rapidly developed solutions are usually optimized for meeting the success criteria with minimized guessed risks rather than for least cost. So, one must keep track of all of the unoptimized processes that accumulate in development as well as their associated cost and all of the guessed risks and devise plans to test for and eliminate the guessed risks and optimize the process for least cost and highest success rate.

Ideal Zener

Zener diodes are handy devices which can be inserted into a circuit in reverse to clamp voltages to desired levels. But like all circuit components, Zener diodes do nor exhibit ideal behavior in all circumstances. The zener voltage varies significantly based upon temperature and through current, for instance. Thus, if one wants to use a zener diode to protect a low voltage, sensitive chip from over voltage on VDD, there are some important considerations. Assuming we have a 3.3V VDD and we select a 3.3Vz Zener diode. The diode Vz will increase with through current, but will decrease with increasing temperature. It is easy and wise to eliminate the current variability by using overcurrent protection devices like PPTC fuses, sized such that current through the zener diode does not exceed the power dissipation limit of the component nor cause the Vz to rise above the voltage maximim of the chip to be protected, whichever of those occurs first as current rises.

A more difficult to handle concern is the tendency of the zener voltage to decrease with temperature. If the curcuit is designed to operate in a wide range of temperatures, then the actual zener voltage has to assessed for all of those temperatures, most crucially to insure that the reduced zener voltage does not fall below the minimum voltage required by the chip, and that there are no other negative effects from reduced VDD (such as how it affects adc reference or digital output voltage).

In extreme cases, where zener protection is needed, but zener voltage variance is undesired, it becomes necessary to use a feedback controlled mosfet with a voltage reference that is temperature stable within the desired operating range, rather than a normal zener. The source of the n-channel mosfet is connected to ground, and the drain is connected to the VDD to be protected. The output of an opamp is connected to the mosfet gate, and the mosfet drain is connected to the + input of the opamp. The temperature stable voltage reference is connected to the negative input if the opamp. Thus if VDD falls below Vref, then the gate voltage will be brought low, making the mosfet high impedance. And if VDD rises above VRef the gate voltage will increase until it sets the mosfet impedance at the exact level required to reduce VDD to match Vref.

Amusingly, a temperature stable voltage reference can itself be made with a temperature feedback controlled current source through a zener diode.

Supercap Buck Converter

There are some obvious advantages to using supercaps in buck converter designs including low output voltage impedance and high output currents. But those same advantages also effect the circuit design.

Ideally, with a supercap, the charging happens on a time scale such that it would be possible to just connect the input voltage to the cap, monitor the cap voltage, and then disconnect the input voltage at the desired cap voltage. However, in practice, this method draws high currents from the input requiring an expensive high watt power supply and beefy cabling or traces. So, putting an inductor and a transistor switch in series with the input is desired, just as they would be used in a standard buck converter. But in the case of a supercap buck, the inductor is there just to limit the input current to levels that are tolerable for all of the components. The power throughput of the buck, then, is dominated by the inductor selection.

One should choose a current rating for the transistor switch and shunt reverse diode to be greater than the input power supply current rating, and the current rating of the inductor should be greater than twice the input power supply rating, then select an inductance and PWM switching frequency such that at a 50% duty cycle, the integral for the first half (when the switch is “on”) of a PWM period of the inductor current divided by a whole PWM period reaches 80% of the power supply max continuous current (more current will flow through the inductor after the transistor is switched off, but that current will come from the reverse diode rather than the input power). This process often requires a few iterations as both the available PWM frequencies and available inductances are often restricted. When calculating inductor current it is safest to assume that the cap voltage is always set to zero to account for the possibility of a very low impedance load on the secondary. The PWM output to the transistor switch gate is, of course, enabled/disabled by voltage feedback to the controller, which will limit the cap voltage to the desired level.

For the capacitor, I suggest the use of Licap 350F or 3000F cells to insure maximum power delivery to your coil gun, I mean… to your safe and beneficial application.

Depletion MOSFET Current Limiter

N-channel depletion MOSFETS can be used for more than just low power current limiting.  The following is an example of an approximately 10A bidirectional current limiter suitable for use in 24V circuits.  One thing to note, of course, is that this circuit is large, with a 12W resistor and two transistors requiring heat sinks, and expensive.

Depletion MOSFET Current Limiter.png

Low Power Circuit Protection

Low power circuit protection devices are important for making durable and long lasting electronic circuits.  Resettable fuses, also called PPTC devices, are made of special PTC materials that maintain a low resistance up to a certain through current.  Once that current level is reached, the PPTC begins to heat up and the resistance jumps to very high levels, stopping current flow and interrupting the circuit.  The fuse then starts to cool and if the fault has been removed the circuit goes back to operating normally, but if the fault remains the PPTC settles at some high resistance that permits just enough current to heat the fuse and maintain the tripped state.

PPTC’s are handy for enclosed or sealed electronics where fuse replacement is too labor intensive or impossible. However, there is another option. N-channel depletion mosfets limit their drain to source current when the gate voltage drops to a certain level below the source voltage. Thus, by connecting the gate of a depletion mosfet to the other side of a source resistor, the transistor becomes increasingly more current limiting as the current from drain to source increases. Thus, the transistor permits current to flow freely until it reaches a trip level and then it clamps the current at the trip level. With their built in source to drain diode action, this transistor only permits current limitation in one direction. However by attaching the source of another n channel depletion mosfet on the other side of the resistor such that the current flows drain to source to resistor to source to drain, and the gates of the transistors are connected to the drains of the other transistor, a bidirectional automatic current limiting device can be created. Using this type of circuit protection requires special attention to how much power is being lost to heat in the transistors, which is a function of the voltage across the device. As such, voltage limiting circuitry may also be required for effective, reusable circuit protection.

Xilinx zynq-7000 and iCE40

Looking through what’s new on Mouser, I came across an advert for the Xilinx zynq-7000 SoC.  These systems on a chip combine a processor with a massive FPGA.  FPGA’s are useful for performing complex logic operations at the highest speeds.  Processors can do the same logic operations as FPGA’s, but they have to break them into multiple simpler operations which use memory and require hundreds to millions of clock cycles.  FPGA’s, on the other hand, can do the same operation in just a few clock cycles.

By combining an FPGA with a processor, as in these zynq-7000’s one is able to effectively use the FPGA to give the processor the ability to perform extremely complex logic operations at FPGA speeds.  Furthermore, as the FPGA’s are programmable, it is possible to “retool” the FPGA in between blocks of high quantities of similar complex logic operations.  This “retooling” takes some time, but there is the potential for a massive time savings overall.  One of the best applications for this SoC, in my opinion, is for applications involving a lot of data stream processing such as feature identification and tracking in video or audio streams.

The Lattice iCE40 series of FPGA’s are not SoC’s and are much smaller FPGA’s in terms of LUT’s as compared to the FPGA’s built into the zynq-7000’s.  But, the iCE40 FPGA’s are considerably cheaper.  Nevertheless, one can use the iCE40’s in combination with an spi flash chip and cheap microcontroller to build a cheap module with a very modest fraction of the zynq-7000’s capabilities.